1. Field of the Invention
The present invention generally relates to bus control circuits for controlling an input and output bus (system-to-external bus) in a semiconductor device such as a microprocessor or a semiconductor memory device fabricated in the form of an IC chip and, more particularly, to a bus control circuit adapted to a variety of types of system-to-external bus protocol control.
2. Description of the Related Art
FIG. 18 is a block diagram showing a construction of a data processing system in which a bus control circuit according to the related art is used. The data processing system comprises a microprocessor 1, an external device 2, a system-to-external bus 3, a CPU unit 11, a memory unit 12, a system-to-external bus control unit 13 according to the related art, an address bus 21, a data bus 22, a control signal line 23, a SEL signal line 23a, an RS signal line 23b and a WS signal line 23c. 
A description will now be given of the operation according to the related art.
The microprocessor 1 communicating with the external device 2 via the system-to-external bus 3 is required to adapt to a variety of system-to-external bus control protocols depending on the type of the external device 2 connected via the system-to-external bus 3. In order to meet the requirement, the system-to-external bus control unit 13 adapted to the target type of system-to-external bus control is designed for each external device 2 connected to the microprocessor 1. Using the system-to-external bus control unit 13 thus designed, an entire set of system-to-external bus control signals including a SEL signal, an RS signal and a WS signal are generated for respective cycles of a system-to-external communication period (N cycle) so that the signals are output to the SEL signal line 23a, the RS signal line 23b and the WS signal line 23c, respectively.
The control of the system-to-external bus 3 is described in various publications. Japanese Laid-Open Patent Application No. 8-292928, Japanese Laid-Open Patent Application 2-280263 and Japanese Laid-Open Patent Application No. 2-85951 disclose a type of control adapted to idle clocks used in communication with the external device 2. Japanese Laid-Open Patent Application No. 3-52350, Japanese Laid-Open Patent Application No. 64-68154 disclose a type of control adapted to a specific communications protocol. Japanese Laid-Open Patent Application No. 57-133741 and Published Japanese Translation of PCT International publication for Patent Application No. 7-502614 disclose a type of control adapted to synchronous communication.
The microprocessor 1 used with the system-to-external bus control unit of the related art as described above must be designed to adapt to a type of protocol required for the external device 2 connected to the microprocessor 1 via the system-to-external bus 3. If the type of control exercised via the system-to-external bus 3 differs, the microprocessor 1 should be redesigned accordingly to adapt to the protocol required for the external device 2. Accordingly, there is a disadvantage in that an extensive period of time is required for redesign. Moreover, the merit of using the microprocessor 1 as a general-purpose semiconductor device is lost and the production cost is increased by having to prepare a variety of products.
Accordingly, a general object of the present invention is to provide a bus control circuit in which the aforementioned disadvantages are eliminated.
Another and more specific object is to provide a bus control circuit capable of generating system-to-external bus control signals in a programmable manner in response to a variety of requirements in system-to-external bus control.
The aforementioned objects can be achieved by a bus control circuit for use in a semiconductor device communicating with an external device via a system-to-external bus, for effecting timing control of the system-to-external bus, comprising: cycle registers provided for respective cycles that occur during communication with the system-to-external bus and provided with signal level areas for holding signal levels of respective system-to-external bus control signals; and a default register provided with normal level areas each holding a signal level of the corresponding system-to-external bus control signal in a normal state, wherein the signal levels of the system-to-external bus control signals held in the corresponding signal level areas in the cycle registers are output according to a predetermined schedule demanded by an arrangement of the signal level areas, and the signal levels of the system-to-external bus control signals held in the corresponding normal level areas in the default register are output when the normal state takes over.
Each of the signal level areas in the corresponding cycle register may hold the signal level of the system-to-external bus control signal in one cycle, and the signal levels of the system-to-external bus control signals held in the corresponding signal level areas in the cycle registers may be output cycle by cycle during the communication.
Each of the signal level areas in the corresponding cycle register may hold the signal level of the system-to-external bus control signal in a half cycle, and the signal levels of the system-to-external bus control signals held in the corresponding signal level areas in the cycle registers may be output half cycle by half cycle during the communication.
Two cycle registers may be provided for each cycle that occurs during the communication, the signal level areas in one of the two cycle registers holding the signal levels in a first half cycle and the signal level areas in the other of the two cycle registers holding the signal levels in a second half cycle.
In each of the cycle registers responsible for respective cycles, two signal level areas may be provided to correspond to the corresponding system-to-external bus control signal, one of the two signal level areas holding the signal level in a first half cycle and the other of the two signal level areas holding the signal level in a second half cycle.
The bus control circuit may further comprise a control register for holding information for controlling timing of output from the cycle registers, wherein the signal levels held in the corresponding signal level areas in the cycle registers are output in accordance with the information held in the control register.
A delay information area for holding delay information specifying a delay to be imposed on the corresponding signal level may be provided for each of the signal level areas in the corresponding cycle register, so that each of the signal levels of the corresponding system-to-external bus control signal held in the corresponding signal level area is delayed, before being output, in accordance with the delay information held in the corresponding delay information area.
Each of the cycle registers may be provided with an instruction field for holding an instruction specifying a method of output of the corresponding signal levels, so that the signal levels of the system-to-external bus control signals held in the signal level areas in the corresponding cycle register are output in accordance with the method of output specified by the instruction held in the instruction field.
Each of the cycle registers and the default register may be provided with undefined signal areas for holding the signal levels of undefined general-purpose signals, so that the signal levels of the general purpose signals held in the undefined signal areas are output in addition to the signal levels of the system-to-external bus control signals held in the signal level areas.